The present invention relates to a computer system and, more specifically, to saving power in a computer system by changing the frequency of the clock signals in the computer system.
In a computer system including a PC or server system equipped, saving power is an important factor in reducing the load on, for example, a power source, air conditioner or cooling device. In order to do so, as shown, for example, in Japanese PCT Application No. 2009-545048, Japanese Patent Publication No. 2008-217628 and Patent Publication No. 2009-128107, conditions such as the load, capacity utilization rate, and temperature (generated heat) of, for example, a CPU/GPU are monitored, and power saving actively realized in accordance with these conditions.
In this case, CPU/GPU capacity utilization is usually monitored by measuring the idle process percentage using software, and performing control according to capacity utilization using software. The control target can be dropping the frequency of the entire IC chip, or dropping the voltage of the power supply.
The method of the prior art is very effective at reducing power consumption, but it also causes the performance of the entire IC chip to drop. This causes problems such as a drop in performance by a bus master device other than the CPU.